816 search results - page 94 / 164 » Interconnect design methods for memory design |
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
SC
2009
ACM
14 years 11 days ago
2009
ACM
In order to understand the complex physics of mother nature, physicist often use many approximations to understand one area of physics and then write a simulation to reduce these ...
VISSYM
2007
13 years 10 months ago
2007
We present a set of techniques and design principles for the visualization of large dynamic software logs consisting of attributed change events, such as obtained from instrumenti...
ISPD
2012
ACM
12 years 3 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...