731 search results - page 11 / 147 » Interconnect modeling for improved system-level design optim... |
CDC
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract-- Communication networks provide a larger flexibility with respect to the control design of large-scale interconnected systems by allowing the information exchange between...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case stud...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
MEMOCODE
2003
IEEE
14 years 24 days ago
2003
IEEE
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...