731 search results - page 13 / 147 » Interconnect modeling for improved system-level design optim... |
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
Communication plays a crucial role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to simpli...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
ISQED
2002
IEEE
14 years 14 days ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
This paper presents one MEMS design tool with total six design flows, which makes it possible that the MEMS designers are able to choose the most suitable design flow for their sp...