731 search results - page 32 / 147 » Interconnect modeling for improved system-level design optim... |
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
ISPD
2003
ACM
14 years 26 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
GLVLSI
1998
IEEE
13 years 12 months ago
1998
IEEE
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those prop...
NOCS
2008
IEEE
14 years 2 months ago
2008
IEEE
—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...