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DAC
2003
ACM
14 years 22 days ago
Realizable RLCK circuit crunching
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...
Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Isma...
ICC
1997
IEEE
13 years 11 months ago
Performance Models for Multiplexed VBR MPEG Video Sources
: This paper performs issues relative to modeling of VBR MPEG coded video sources over ATM B-ISDN networks. Firstly, we analyse the statistical characteristics of the three types o...
Nikolaos D. Doulamis, Anastasios D. Doulamis, Geor...
CGO
2007
IEEE
14 years 1 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
ICCAD
2003
IEEE
142views Hardware» more  ICCAD 2003»
14 years 4 months ago
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
The recent demand for system-on-chip RF mixed-signal design and aggressive supply-voltage reduction require chip-level accurate analysis of both the substrate and power delivery s...
Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Ch...
ACMSE
1992
ACM
13 years 11 months ago
Disk performance enhancement through Markov-based cylinder remapping
A scheme for disk subsystem performance enhancement that is based on (virtual) cylinder remapping is proposed. A natural workload on a real system is measured, and statistical tes...
Robert Geist, Darrell Suggs, Robert G. Reynolds, S...