Sciweavers

44 search results - page 4 / 9
» Intrabody Buses for Data and Power
Sort
View
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
14 years 21 days ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
HPCA
2005
IEEE
14 years 1 months ago
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
With technology scaling, power dissipation and localized heating in global and semi-global bus wires are becoming increasingly important, and this necessitates the development of ...
Krishnan Sundaresan, Nihar R. Mahapatra
DAC
2001
ACM
14 years 8 months ago
Coupling-Driven Bus Design for Low-Power Application-Specific Systems
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
Youngsoo Shin, Takayasu Sakurai
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 2 months ago
MPSoCs run-time monitoring through Networks-on-Chip
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
Leandro Fiorin, Gianluca Palermo, Cristina Silvano