108 search results - page 12 / 22 » Introspective 3D chips |
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch Through-Silicon Via (TSV) for advanced interconnections. The ...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Interconnection plays an important role in performance and power of CMP designs using deep sub-micron technology. The network-on-chip (NoCs) has been proposed as a scalable and hi...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
ISCAS
2006
IEEE
2006
IEEE
Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures
14 years 1 months ago
— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release proce...