Sciweavers

108 search results - page 17 / 22
» Introspective 3D chips
Sort
View
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
13 years 12 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ISBI
2007
IEEE
14 years 1 months ago
Real-Time Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridhar...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 11 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ICCAD
2007
IEEE
128views Hardware» more  ICCAD 2007»
14 years 4 months ago
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar
ISCAS
2007
IEEE
172views Hardware» more  ISCAS 2007»
14 years 1 months ago
A 70dB Gain Low-Power Band-Pass Amplifier for Bio-Signals Sensing Applications
— this paper presents an integrated 70dB gain, low-power, and low-noise active RC amplifier and filter for low bio-signals sensing applications. The -3dB sense channel bandwidth ...
Cheng Chih Liu