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» Large-scale capacitance calculation
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GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
14 years 20 days ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
13 years 11 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
DATE
2010
IEEE
140views Hardware» more  DATE 2010»
14 years 14 days ago
Variation-aware interconnect extraction using statistical moment preserving model order reduction
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...
Tarek A. El-Moselhy, Luca Daniel
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 5 months ago
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
With the adoption of ultra regular fabric paradigms for controlling design printability at the 22nm node and beyond, there is an emerging need for a layout-driven, pattern-based p...
Tarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Dani...
IEEECIT
2006
IEEE
14 years 1 months ago
An Energy-Efficient Localization Scheme with Specified Lower Bound for Wireless Sensor Networks
Localization is a basic and critical requirement for wireless sensor network applications, e.g. target tracking, monitoring and intrusion detection. In the received signal strengt...
Haoran Feng, Ruixi Yuan, Chundi Mu