Sciweavers

384 search results - page 7 / 77
» Latch Modeling for Statistical Timing Analysis
Sort
View
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 4 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 4 months ago
An accurate sparse matrix based framework for statistical static timing analysis
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important th...
Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh,...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
14 years 2 months ago
Use of statistical timing analysis on real designs
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gr...
ICCAD
2008
IEEE
125views Hardware» more  ICCAD 2008»
14 years 4 months ago
Practical, fast Monte Carlo statistical static timing analysis: why and how
Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the appr...
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 1 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov