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DATE
2005
IEEE
124views Hardware» more  DATE 2005»
14 years 28 days ago
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
Raoul F. Badaoui, Ranga Vemuri
EH
2004
IEEE
125views Hardware» more  EH 2004»
13 years 11 months ago
Routine High-Return Human-Competitive Evolvable Hardware
This paper reviews the use of genetic programming as an automated invention machine for the synthesis of both the topology and sizing of analog electrical circuits. The paper focu...
John R. Koza, Martin A. Keane, Matthew J. Streeter
ISCAS
2002
IEEE
113views Hardware» more  ISCAS 2002»
14 years 7 days ago
Cell library for automatic synthesis of analog error control decoders
This paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog error control decoders can be automatically synthesi...
Jie Dai, Chris Winstead, Chris J. Myers, Reid R. H...
ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
14 years 27 days ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
DAC
2003
ACM
14 years 17 days ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich