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» Leakage Current Reduction in VLSI Systems
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ISVLSI
2002
IEEE
81views VLSI» more  ISVLSI 2002»
14 years 16 days ago
Impact of Technology Scaling in the Clock System Power
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
14 years 13 days ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
GLVLSI
2007
IEEE
134views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Sleep transistor distribution in row-based MTCMOS designs
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
Chanseok Hwang, Peng Rong, Massoud Pedram
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
CASES
2006
ACM
14 years 1 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks