491 search results - page 13 / 99 » Leakage power modeling and optimization in interconnection n... |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
EENERGY
2010
13 years 8 months ago
2010
PATMOS
2007
Springer
14 years 2 months ago
2007
Springer
Abstract. Until now, the great majority of research in low-power systems has assumed a convex power model. However, recently, due to the confluence of emerging technological and ar...
ISPD
2012
ACM
12 years 3 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ASPDAC
2009
ACM
14 years 20 days ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...