491 search results - page 15 / 99 » Leakage power modeling and optimization in interconnection n... |
ICPP
2000
IEEE
14 years 11 days ago
2000
IEEE
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
PATMOS
2007
Springer
14 years 2 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
ASPLOS
2010
ACM
13 years 11 months ago
2010
ACM
We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelengthbased routing, where the route followed by a packe...