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» Leakage power modeling and reduction with data retention
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ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
14 years 5 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
CASES
2006
ACM
14 years 2 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
WISA
2009
Springer
14 years 3 months ago
A Comparative Study of Mutual Information Analysis under a Gaussian Assumption
In CHES 2008 a generic side-channel distinguisher, Mutual Information, has been introduced to be independent of the relation between measurements and leakages as well as between le...
Amir Moradi, Nima Mousavi, Christof Paar, Mahmoud ...
ISCA
2012
IEEE
261views Hardware» more  ISCA 2012»
11 years 11 months ago
RAIDR: Retention-aware intelligent DRAM refresh
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu
ISLPED
2007
ACM
123views Hardware» more  ISLPED 2007»
13 years 10 months ago
A low-power SRAM using bit-line charge-recycling technique
We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtain...
Keejong Kim, Hamid Mahmoodi, Kaushik Roy