137 search results - page 5 / 28 » Leakage power modeling and reduction with data retention |
CHES
2003
Springer
14 years 1 months ago
2003
Springer
We introduce multi-channel attacks, i.e., side-channel attacks which utilize multiple side-channels such as power and EM simultaneously. We propose an adversarial model which combi...
ETS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. ...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
JCSC
2002
13 years 8 months ago
2002
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...