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IACR
2011
128views more  IACR 2011»
12 years 8 months ago
Sign Modules in Secure Arithmetic Circuits
In this paper, we study the complexity of secure multiparty computation using only the secure arithmetic black-box of a finite field, counting the cost by the number of secure m...
Ching-Hua Yu
DATE
1999
IEEE
134views Hardware» more  DATE 1999»
14 years 27 days ago
Verifying Imprecisely Working Arithmetic Circuits
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
Michaela Huhn, Klaus Schneider, Thomas Kropf, Geor...
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
14 years 2 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
APCSAC
2003
IEEE
14 years 1 months ago
Arithmetic Circuits Combining Residue and Signed-Digit Representations
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
Anders Lindström, Michael Nordseth, Lars Beng...
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 10 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh