239 search results - page 23 / 48 » Lectures on VLSI and Integrated Circuit Design |
134
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GLVLSI
2009
IEEE
15 years 11 months ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
117
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GLVLSI
2010
IEEE
15 years 9 months ago
2010
IEEE
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
134
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GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
199
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ISPD
2012
ACM
13 years 11 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
137
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JETC
2008
15 years 2 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...