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INFOCOM
2000
IEEE
14 years 2 months ago
A QoS-Aware Multicast Routing Protocol
—The future Internet is expected to support multicast applications with quality of service (QoS) requirements. To facilitate this, QoS multicast routing protocols are pivotal in ...
Shigang Chen, Klara Nahrstedt, Yuval Shavitt
ISPD
1999
ACM
127views Hardware» more  ISPD 1999»
14 years 1 months ago
Buffer insertion for clock delay and skew minimization
 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
X. Zeng, D. Zhou, Wei Li
CGO
2009
IEEE
14 years 1 months ago
Alchemist: A Transparent Dependence Distance Profiling Infrastructure
Effectively migrating sequential applications to take advantage of parallelism available on multicore platforms is a well-recognized challenge. This paper addresses important aspec...
Xiangyu Zhang, Armand Navabi, Suresh Jagannathan
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
EUROPAR
2000
Springer
14 years 1 months ago
Ahnentafel Indexing into Morton-Ordered Arrays, or Matrix Locality for Free
Abstract. Definitions for the uniform representation of d-dimensional matrices serially in Morton-order (or Z-order) support both their use with cartesian indices, and their divide...
David S. Wise