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IPCCC
2006
IEEE
14 years 28 days ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
EUROPAR
2003
Springer
14 years 4 days ago
FOBS: A Lightweight Communication Protocol for Grid Computing
The advent of high-performance networks in conjunction with low-cost, powerful computational engines has made possible the development of a new set of technologies termed computat...
Phillip M. Dickens
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
14 years 3 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ISM
2008
IEEE
111views Multimedia» more  ISM 2008»
14 years 1 months ago
Secure and Low Cost Selective Encryption for JPEG2000
Selective encryption is a new trend in content protection. It aims at reducing the amount of data to encrypt while achieving a sufficient and inexpensive security. This approach ...
Ayoub Massoudi, Frédéric Lefè...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...