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TC
2011
13 years 2 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
TASE
2010
IEEE
13 years 2 months ago
Clear and Precise Specification of Ecological Data Management Processes and Dataset Provenance
Abstract--With the availability of powerful computational and communication systems, scientists now readily access large, complicated derived datasets and build on those results to...
Leon J. Osterweil, Lori A. Clarke, Aaron M. Elliso...
SPAA
2006
ACM
14 years 1 months ago
Astronomical real-time streaming signal processing on a Blue Gene/L supercomputer
LOFAR is the first of a new generation of radio telescopes, that combines the signals from many thousands of simple, fixed antennas, rather than from expensive dishes. Its revol...
John W. Romein, P. Chris Broekema, Ellen van Meije...
CODES
2005
IEEE
14 years 1 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...