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DAC
2003
ACM
14 years 8 months ago
Partial task assignment of task graphs under heterogeneous resource constraints
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tas...
Radoslaw Szymanek, Krzysztof Kuchcinski
DAC
2003
ACM
14 years 8 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
VLSID
2007
IEEE
126views VLSI» more  VLSID 2007»
14 years 8 months ago
An ECO Technique for Removing Crosstalk Violations in Clock Networks
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
Amit Kumar, Krishnendu Chakrabarty, Chunduri Rama ...
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
14 years 2 days ago
A Language for Describing Predictors and Its Application to Automatic Synthesis
As processor architectures have increased their reliance on speculative execution to improve performance, the importance of accurate prediction of what to execute speculatively ha...
Joel S. Emer, Nicholas C. Gloy
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
14 years 2 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha