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VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 8 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
RECOMB
2006
Springer
14 years 8 months ago
Inferring Gene Orders from Gene Maps Using the Breakpoint Distance
Abstract. Preliminary to most comparative genomics studies is the annotation of chromosomes as ordered sequences of genes. Unfortunately, different genetic mapping techniques usual...
Guillaume Blin, Eric Blais, Pierre Guillon, Mathie...
SODA
2010
ACM
155views Algorithms» more  SODA 2010»
14 years 5 months ago
A Space--Time Tradeoff for Permutation Problems
Many combinatorial problems--such as the traveling salesman, feedback arcset, cutwidth, and treewidth problem-can be formulated as finding a feasible permutation of n elements. Ty...
Mikko Koivisto, Pekka Parviainen
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 5 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
ICCD
2001
IEEE
103views Hardware» more  ICCD 2001»
14 years 5 months ago
Fixed-outline Floorplanning through Better Local Search
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
Saurabh N. Adya, Igor L. Markov