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» Load balancing using dynamic cache allocation
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ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
14 years 1 months ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
14 years 2 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
IMC
2010
ACM
13 years 5 months ago
YouTube traffic dynamics and its interplay with a tier-1 ISP: an ISP perspective
In this paper we conduct an extensive and in-depth study of traffic exchanged between YouTube data centers and its users, as seen from the perspective of a tier-1 ISP in Spring 20...
Vijay Kumar Adhikari, Sourabh Jain, Zhi-Li Zhang
IPPS
1998
IEEE
13 years 12 months ago
Dynamic Processor Allocation with the Solaris Operating System
The Loop-Level Process Control LLPC policy 9 dynamically adjusts the number of threads an application is allowed to execute based on the application's available parallelism a...
Kelvin K. Yue, David J. Lilja
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
13 years 11 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park