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» Logic as Energy: A SAT-Based Approach
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WABI
2007
Springer
14 years 3 months ago
Predicting Protein Folding Kinetics Via Temporal Logic Model Checking
Christopher James Langmead⋆ and Sumit Kumar Jha Department of Computer Science, Carnegie Mellon University We present a novel approach for predicting protein folding kinetics us...
Christopher James Langmead, Sumit Kumar Jha
CODES
2003
IEEE
14 years 3 months ago
A codesigned on-chip logic minimizer
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
Roman L. Lysecky, Frank Vahid
CSREAESA
2003
13 years 11 months ago
Common Mistakes in Adiabatic Logic Design and How to Avoid Them
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
Michael P. Frank
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
13 years 1 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
DAC
2001
ACM
14 years 10 months ago
A True Single-Phase 8-bit Adiabatic Multiplier
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthy...