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» Logic design for low-voltage low-power CMOS circuits
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GLVLSI
2003
IEEE
229views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Design issues in low-voltage high-speed current-mode logic buffers
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
Payam Heydari
ICCD
2007
IEEE
159views Hardware» more  ICCD 2007»
14 years 5 months ago
CMOS logic design with independent-gate FinFETs
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device charact...
Anish Muttreja, Niket Agarwal, Niraj K. Jha
ISCAS
2005
IEEE
140views Hardware» more  ISCAS 2005»
14 years 2 months ago
Low energy asynchronous architectures
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Ilya Obridko, Ran Ginosar
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 2 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Novel dual-Vth independent-gate FinFET circuits
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
Masoud Rostami, Kartik Mohanram