233 search results - page 23 / 47 » Logic design for low-voltage low-power CMOS circuits |
ICCAD
1997
IEEE
14 years 25 days ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
ARVLSI
2001
IEEE
14 years 8 days ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
DFT
2000
IEEE
14 years 1 months ago
2000
IEEE
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
GLVLSI
2009
IEEE
13 years 12 months ago
2009
IEEE
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...