233 search results - page 30 / 47 » Logic design for low-voltage low-power CMOS circuits |
DAC
2011
ACM
12 years 8 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
ASPDAC
2005
ACM
14 years 2 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...
TVLSI
2002
13 years 8 months ago
2002
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
ET
2002
13 years 8 months ago
2002
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
FCCM
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...