233 search results - page 33 / 47 » Logic design for low-voltage low-power CMOS circuits |
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
ISLPED
2009
ACM
14 years 1 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
GLVLSI
1999
IEEE
14 years 28 days ago
1999
IEEE
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...