233 search results - page 35 / 47 » Logic design for low-voltage low-power CMOS circuits |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
— When exploring computing elements made from technologies other than CMOS, it is imperative to investigate the effects of physical implementation constraints. This paper focuses...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...