233 search results - page 4 / 47 » Logic design for low-voltage low-power CMOS circuits |
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static nois...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
ISLPED
2003
ACM
14 years 21 days ago
2003
ACM
The increasing prominence of portable systems and the need to limit power consumption and hence, heat dissipation in very high density VLSI chips have led to rapid and innovative ...