132 search results - page 20 / 27 » Logic for Automated Mechanism Design - A Progress Report |
DAC
2008
ACM
14 years 7 months ago
2008
ACM
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
TPHOL
2007
IEEE
14 years 1 months ago
2007
IEEE
Formal, modular, and mechanized verification of realistic systems code is desirable but challenging. Verification of machine context management (a basis of multi-tasking) is one ...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
One of the main goals of coverage tools is to provide the user with informative presentation of coverage information. Specifically, information on large, cohesive sets of uncovere...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
FPL
2004
Springer
14 years 3 days ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...