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ATS
2005
IEEE
91views Hardware» more  ATS 2005»
14 years 1 months ago
SOC Test Scheduling with Test Set Sharing and Broadcasting
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
13 years 11 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 7 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 12 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba
ICCD
1992
IEEE
83views Hardware» more  ICCD 1992»
13 years 11 months ago
Logical Verification of the NVAX CPU Chip Design
ct Digital's NVAX high-performance microprocessor has a complex logical design. A rigorous simulation-based verification effort was undertaken to ensure that there were no log...
Walker Anderson