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ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
14 years 24 days ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
14 years 1 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
SAC
2009
ACM
14 years 2 months ago
Network protocol interoperability testing based on contextual signatures and passive testing
This paper presents a methodology for interoperability testing based on contextual signatures and passive testing with invariants. The concept of contextual signature offers a fra...
Fatiha Zaïdi, Emmanuel Bayse, Ana R. Cavalli
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 11 months ago
Testing of Quantum Dot Cellular Automata Based Designs
There has been considerable research on quantum dots cellular automata as a new computing scheme in the nano-scale regimes. The basic logic element of this technology is a majorit...
Mehdi Baradaran Tahoori, Fabrizio Lombardi
HASE
2007
IEEE
14 years 1 months ago
Advances in Quantum Computing Fault Tolerance and Testing
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustr...
David Y. Feinstein, V. S. S. Nair, Mitchell A. Tho...