980 search results - page 19 / 196 » Logical Testing |
ETS
2011
IEEE
12 years 7 months ago
2011
IEEE
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
EUROGP
2000
Springer
13 years 11 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
EURODAC
1990
IEEE
13 years 11 months ago
1990
IEEE
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...