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DATE
2000
IEEE
136views Hardware» more  DATE 2000»
14 years 1 days ago
On Applying Incremental Satisfiability to Delay Fault Testing
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah...
TSE
2010
155views more  TSE 2010»
13 years 2 months ago
Incremental Test Generation for Software Product Lines
Recent advances in mechanical techniques for systematic testing have increased our ability to automatically find subtle bugs, and hence to deploy more dependable software. This pap...
Engin Uzuncaova, Sarfraz Khurshid, Don S. Batory
MTV
2006
IEEE
98views Hardware» more  MTV 2006»
14 years 1 months ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, archite...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy...
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
14 years 17 days ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
CP
1998
Springer
13 years 12 months ago
Generation of Test Patterns for Differential Diagnosis of Digital Circuits
In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rathe...
Francisco Azevedo, Pedro Barahona