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PATMOS
2004
Springer
14 years 3 months ago
Signal Sampling Based Transition Modeling for Digital Gates Characterization
Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gat...
Alejandro Millán, Jorge Juan-Chico, Manuel ...
ASYNC
2003
IEEE
119views Hardware» more  ASYNC 2003»
14 years 3 months ago
Asynchronous DRAM Design and Synthesis
We present the design of a high performance on-chip pipelined asynchronous DRAM suitable for use in a microprocessor cache. Although traditional DRAM structures suffer from long a...
Virantha N. Ekanayake, Rajit Manohar
GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
14 years 3 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
ISCAS
2003
IEEE
175views Hardware» more  ISCAS 2003»
14 years 2 months ago
Analysis of timing jitter in ring oscillators due to power supply noise
∑= += N i firiT 1 0 )( ττ (1) This paper presents a time-domain method for estimating the jitter in ring oscillators that is due to power supply noise. The method is used to a...
Tony Pialis, Khoman Phang
ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
14 years 2 months ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou