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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 12 months ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
ISCAS
2006
IEEE
70views Hardware» more  ISCAS 2006»
15 years 12 months ago
Quadrature mismatch shaping with a complex, tree structured DAC
— Quadrature Σ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the...
Stijn Reekmans, Jeroen De Maeyer, Pieter Rombouts,...
ISCC
2006
IEEE
129views Communications» more  ISCC 2006»
15 years 12 months ago
A Semantic Overlay Network for P2P Schema-Based Data Integration
Abstract— Today data sources are pervasive and their number is growing tremendously. Current tools are not prepared to exploit this unprecedented amount of information and to cop...
Carmela Comito, Simon Patarin, Domenico Talia
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
15 years 12 months ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
GLVLSI
2005
IEEE
147views VLSI» more  GLVLSI 2005»
15 years 11 months ago
1-V 7-mW dual-band fast-locked frequency synthesizer
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen