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FPGA
2000
ACM
161views FPGA» more  FPGA 2000»
13 years 11 months ago
The effect of LUT and cluster size on deep-submicron FPGA performance and density
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
Elias Ahmed, Jonathan Rose
PADS
1998
ACM
14 years 12 days ago
Event History Based Sparse State Saving in Time Warp
This paper presents a sparse state saving scheme for Time Warp parallel discrete event simulation. The scheme bases the selection of the states to be recorded on the event history...
Francesco Quaglia
ICCD
2008
IEEE
119views Hardware» more  ICCD 2008»
14 years 5 months ago
Hierarchical simulation-based verification of Anton, a special-purpose parallel machine
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
John P. Grossman, John K. Salmon, Richard C. Ho, D...
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
14 years 2 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
14 years 8 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu