1307 search results - page 114 / 262 » Low Power Hardware for a High Performance PDA |
164
click to vote
ISQED
2009
IEEE
16 years 29 days ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
153
click to vote
DATE
2008
IEEE
16 years 19 days ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
140
click to vote
CF
2006
ACM
16 years 4 days ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
156
click to vote
DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
198
click to vote
ISQED
2006
IEEE
16 years 5 days ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...