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» Low Power Hardware for a High Performance PDA
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FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 11 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
IPSN
2005
Springer
15 years 11 months ago
Perpetual environmentally powered sensor networks
— Environmental energy is an attractive power source for low power wireless sensor networks. We present Prometheus, a system that intelligently manages energy transfer for perpet...
Xiaofan Jiang, Joseph Polastre, David E. Culler
NOCS
2010
IEEE
15 years 4 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...
SBCCI
2009
ACM
187views VLSI» more  SBCCI 2009»
15 years 11 months ago
Design of low complexity digital FIR filters
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
Levent Aksoy, Diego Jaccottet, Eduardo Costa
TVLSI
2002
100views more  TVLSI 2002»
15 years 5 months ago
Architectural strategies for low-power VLSI turbo decoders
Abstract--The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is requir...
Guido Masera, M. Mazza, Gianluca Piccinini, F. Vig...