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ICCD
2004
IEEE
109views Hardware» more  ICCD 2004»
14 years 4 months ago
Low Power Test Data Compression Based on LFSR Reseeding
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
Jinkyu Lee, Nur A. Touba
ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
14 years 1 months ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
14 years 4 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
DATE
2008
IEEE
128views Hardware» more  DATE 2008»
14 years 2 months ago
Robust and Low Complexity Rate Control for Solar Powered Sensors
This paper is concerned with solar driven sensors deployed in an outdoor environment. We present feedback controllers which adapt parameters of the application such that a maximal...
Clemens Moser, Lothar Thiele, Davide Brunelli, Luc...
GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
14 years 27 days ago
CMOS flash analog-to-digital converter for high speed and low voltage applications
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi