1307 search results - page 60 / 262 » Low Power Hardware for a High Performance PDA |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
We designed and fabricated an 8-bit analog-to- LiSTOF ENERGY-SCAVENGER PERFORMANCE digital converter (ADC) in a 0.5,um Silicon-on-Sapphire CMOS technology. The ultra-low power and ...
IPPS
2000
IEEE
14 years 1 days ago
2000
IEEE
This paper examines two Network Interface Card microarchitectures that support low latency, high bandwidth userlevel message passing in multi-user environments. The two are at dif...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...