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ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 1 months ago
Low power SRAM techniques for handheld products
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
Rabiul Islam, Adam Brand, Dave Lippincott
IPPS
2006
IEEE
14 years 1 months ago
A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
Wing On Fung, Tughrul Arslan
APCCAS
2006
IEEE
256views Hardware» more  APCCAS 2006»
14 years 1 months ago
Asynchronous Design Methodology for an Efficient Implementation of Low power ALU
— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...
ICCD
2001
IEEE
86views Hardware» more  ICCD 2001»
14 years 4 months ago
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aima...
ISCAS
2005
IEEE
141views Hardware» more  ISCAS 2005»
14 years 1 months ago
A low voltage CMOS multiplier for high frequency equalization
- This paper describes the design of a low power
Justin P. Abbott, Calvin Plett, John W. M. Rogers