Sciweavers

1307 search results - page 97 / 262
» Low Power Hardware for a High Performance PDA
Sort
View
WSCG
2004
154views more  WSCG 2004»
15 years 7 months ago
Emulating an Offline Renderer by 3D Graphics Hardware
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...
Jörn Loviscach
152
Voted
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
15 years 11 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
EGH
2010
Springer
15 years 4 months ago
Hardware implementation of micropolygon rasterization with motion and defocus blur
Current GPUs rasterize micropolygons (polygons approximately one pixel in size) inefficiently. Additionally, they do not natively support triangle rasterization with jittered samp...
J. S. Brunhaver, Kayvon Fatahalian, Pat Hanrahan
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 11 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
15 years 7 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram