Sciweavers

25 search results - page 2 / 5
» Low Power Realization of FIR Filters Implemented using Distr...
Sort
View
FPL
2003
Springer
146views Hardware» more  FPL 2003»
14 years 21 days ago
Domain-Specific Reconfigurable Array for Distributed Arithmetic
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
Sami Khawam, Tughrul Arslan, Fred Westall
ISCAS
1999
IEEE
116views Hardware» more  ISCAS 1999»
13 years 11 months ago
A coefficient segmentation algorithm for low power implementation of FIR filters
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...
Ahmet T. Erdogan, Tughrul Arslan
CDES
2006
240views Hardware» more  CDES 2006»
13 years 9 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
ISLPED
2000
ACM
111views Hardware» more  ISLPED 2000»
13 years 12 months ago
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels
In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Variou...
Khurram Muhammad, Robert B. Staszewski, Poras T. B...
ERSA
2006
99views Hardware» more  ERSA 2006»
13 years 9 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...