155 search results - page 19 / 31 » Low Power Techniques for Digital GaAs VLSI |
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
ECCTD
2011
12 years 7 months ago
2011
⎯ Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate th...