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» Low Power Testing of VLSI Circuits: Problems and Solutions
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CDC
2010
IEEE
181views Control Systems» more  CDC 2010»
13 years 2 months ago
Relationship between power loss and network topology in power systems
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...
Javad Lavaei, Steven H. Low
ITC
2003
IEEE
156views Hardware» more  ITC 2003»
14 years 27 days ago
A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation
This paper describes a system for performing high precision IDDQ measurement of CMOS ICs having a large peak current during operation. Although the measurement rate is at a low sp...
Nobuhiro Sato, Yoshihiro Hashimoto
DAC
2007
ACM
14 years 8 months ago
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network
High efficiency low voltage DC-DC conversion is a key enabler to the design of power-efficient integrated circuits. Typically a star configuration of the DC-DC converters, where o...
Behnam Amelifard, Massoud Pedram
IJAIT
2010
167views more  IJAIT 2010»
13 years 6 months ago
Bee Colony Optimization with Local Search for Traveling Salesman Problem
Many real world industrial applications involve finding a Hamiltonian path with minimum cost. Some instances that belong to this category are transportation routing problem, scan c...
Li-Pei Wong, Malcolm Yoke-Hean Low, Chin Soon Chon...
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
13 years 12 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo