89 search results - page 3 / 18 » Low Power Testing of VLSI Circuits: Problems and Solutions |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is hi...
DFT
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...