89 search results - page 3 / 18 » Low Power Testing of VLSI Circuits: Problems and Solutions |
206
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
179
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ISQED
2006
IEEE
15 years 11 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
154
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ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
— We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is hi...
169
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DFT
2004
IEEE
15 years 9 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
226
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ARVLSI
1995
IEEE
15 years 9 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...