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ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
15 years 9 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
16 years 4 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
16 years 1 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore
CAL
2008
15 years 4 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
CASCON
1997
74views Education» more  CASCON 1997»
15 years 5 months ago
A high performance get-put interface for ATM communications
This paper describes the implementation of a reliable Get-Put interface written for a distributed memory environment. The asynchronous semantics of the Put as well as the split tr...
Ronald Mraz, Edward Nowicki, Mathew Thoennes